Welcome
The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry, government, research, academia and ecosystem support – that are building the future of innovation on RISC-V.
RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success, with one-third of RISC-V’s global community based in Europe.
RISC-V Summit Europe takes place in Paris from Monday 12th to Thursday 15th May, 2025. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe, and for this reason the conference is designed to help attendees to explore both commercial and research applications. RISC-V Summit Europe is an opportunity not to be missed. Come to Paris to be part of the new wave of European computing innovation!
Summit Overview
Get up to speed on Monday and dive into three days of RISC-V news!
Keynotes & Invited Talks
Learn about the exciting progress of RISC-V across industries and the hardware/software stack from our keynote speakers and invited talks.
RISC-V Technology Update
T1.1.03, Tuesday 13 at 09:15, in Gaston Berger amphitheater (S2).
By Andrea Gallo, RISC-V VP Technology, RISC-V.
(TBD)
T1.1.04, Tuesday 13 at 09:40, in Gaston Berger amphitheater (S2).
By Balaji Baktha, Founder, President, CEO, and Chairman, Ventana.
Abstract: (TBD)
Bio: Balaji Baktha is the founder and CEO of Ventana Micro Systems, a leader in high-performance RISC-V processors. He is an experienced semiconductor executive and a serial technology entrepreneur and investor with a proven track record in founding and exiting several successful startups over more than 30 years in Silicon Valley. Balaji is a board member of RISC-V International as well as several other startups, and a Limited Partner and Senior Advisor at PE and VC funds. Prior to Ventana, Balaji was the founder and CEO of Veloce Technologies, the world’s first 64-bit ARM based high performance processor for cloud-compute (acquired by AppliedMicro). Before Veloce, Balaji was the VP and GM of the Communications Business at Marvell Semiconductor where he managed multiple product groups including compute, wired and wireless networking, and Enterprise Storage SoCs. Before Marvell, Balaji co-founded Platys, a startup that pioneered iSCSI storage networking and was subsequently acquired by Adaptec (now Microsemi). Prior to Platys, Balaji founded Shuttle Technologies (acquired by SCM Micro) to build the first digital media & storage I/O SoCs for Apple, Sony, and HP.
Sovereignty, independence, innovation: 7 years of HW/SW codesign with RISC-V at CEA
T1.1.05, Tuesday 13 at 10:00, in Gaston Berger amphitheater (S2).
By Thomas Dombek, Head of Digital Integrated Circuits and Systems Department, CEA.
Abstract: By ending the epoch of closed, proprietary ISAs, RISC-V has opened a new era of innovation in the computing world. Its open ISA not only enables the tailoring of architecture to various application domains, from performance to low power, and from safety to security, but it also enables new forms of joint initiatives in the design and tools ecosystem. This ranges from new forums of cooperation between industrial competitors in the market, to new models of industry/academic collaboration. The versatility of open ISA specifications, which enables both open-source, public cooperation and also closed-door commercial agreements, will facilitate new kinds of partnerships and unexpected advances in the computing field at large. This talk will provide a return of experience from seven years of commitment to the RISC-V ecosystem and, a peek at key achievements of CEA and its academic and business partners.
Bio: Thomas Dombek is head of the Digital Systems and Integrated Circuits division at CEA LIST (French Atomic Energy Commission), Saclay, France. He received his master’s degrees in engineering from Ecole Centrale de Lyon, France, and in microelectronics from the Technical University of Darmstadt, Germany, in 1998. He has worked over 15 years in the semiconductor industry at various research and management positions within Philips, NXP and ST-Ericsson France. In 2011, he joined CEA LIST, heading research on software, modeling and hardware challenges in smart embedded systems.
Enabling the Next Phase of RISC-V: Product Innovation and Scalable Solutions
T1.1.06, Tuesday 13 at 10:15, in Gaston Berger amphitheater (S2).
By Ning He, SVP and CTO, EWSING.
Abstract: RISC-V has achieved remarkable success in the IoT application and is now expanding into more advanced scenarios. To sustain this growth, a comprehensive product portfolio, mature software support, and systematic large-scale deployments are essential. This presentation highlights how ESWING Computing, a leading innovator in RISC-V, enriches the RISC-V ecosystem through multiple industry-first products while enhancing software capabilities. Additionally, we will showcase how our system-level solutions for vertical industries accelerate the structured adoption and widespread deployment of RISC-V, driving the ecosystem’s rapid evolution.
Bio: Dr. Ning He is the Senior Vice President and Chief Technology Officer of ESWING Computing Technology Co. Ltd, a leading RISC-V products and solutions provider in China. He holds a Bachelor‘s and a Master’s degree from the University of Electronic Science and Technology of China, and a Ph.D. degree in Electrical Engineering from Arizona State University, USA. Prior to joining ESWING, Dr. He served as Vice President and CTO at a company listed on China’s A-share market. With extensive expertise in modem system design, computing architecture, IC product solutions, and technology management, he now leads the development of RISC-V ecosystem and technology platforms at ESWING. Beyond his corporate role, Dr. He actively contributes to industry standardization as the rotating chairman of both the RISC-V Working Committee at the China Electronics Standardization Association and the Zhongguancun Standardization Association, driving the standardization and advancement of RISC-V technologies.
RISC-V State of the Union
T1.3.01, Tuesday 13 at 11:30, in Gaston Berger amphitheater (S2).
By Krste Asanović, Chief Architect, SiFive.
Abstract: In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI. Krste will discuss new developments in the RISC-V ISA, including security extensions and matrix extensions for AI, as well as new profile and platform initiatives.
Bio: Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project at UC Berkeley, serves as chairman of RISC-V International, and cofounded SiFive Inc. to support commercial use of RISC-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.
Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP.
T1.3.04, Tuesday 13 at 12:30, in Gaston Berger amphitheater (S2).
By Wei-Han Lien, Chief Architect and Senior Fellow, Tenstorrent.
Abstract: (TBD)
Bio: Wei-Han Lien is a Chief Architect and Senior Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high performance memory subsystem for the Tenstorrent heterogeneous high-performance computation platform for AI and HPC computing. He is also leading the definition of Tenstorrent’s chiplet architecture for constructing scalable, configurable, and composable SiP with cohesive power management, security, and system management architectural definitions for compatibility. Before joining Tenstorrent, Wei-Han joined Apple through the PA Semi acquisition. He led Apple design team on the microarchitectural definitions of two of the most transformative Apple iPhone/iPad application processors from scratch, the A6 and A7 CPU projects. The Apple A7 CPU core is a solid CPU microarchitecture substrate for future generations of A-series (A7-A14) iPhone/iPad mobile processors and M-series (M1) MacBookPro processors. Before Apple, he was a distinguished architect leading P.A.Semi’s PWRficient PA6T dual O-o-O triple-issue superscalar PowerPC CPU cores. At Raza Microelectronics, he led the microarchitectures of the single-chip 40Gb scalable shared-memory switching chip and distributed-shared-memory cache coherent Ethernet switch. He joined Nexgen and AMD after graduating from the University of Michigan; he was part of a team designing the Nx586 (AMD K6), the most competitive microprocessor product to the Intel Pentium processor from 1997-1999 in the market.
The Custom Silicon Imperative: Addressing Manufacturing and Supply Chain Realities
T1.5.01, Tuesday 13 at 14:30, in Gaston Berger amphitheater (S2).
By Pablo Valerio, Supply Chain section Editor, EETimes.
Abstract: The semiconductor industry faces creative disruption due to the rise of bespoke silicon driven by demands for AI and high-performance computing, where RISC based cores are displacing traditional stakeholders. This trend presents manufacturing and supply chain challenges due to the cost of development and the complexity of international supply chains. Open-source architectures like RISC-V are gaining traction as an alternative, offering customization and potentially reducing reliance on unstable supply chains, particularly in Europe.
Bio: Pablo Valerio is a seasoned engineer with 30+ years of experience. For over 10 years, he has been a contributing editor and analyst for EE Times (where he edits the Supply Chain section). He also wrote for EPSNews, InformationWeek, EBN, LightReading, Network Computing, and IEEE Xplore. His coverage spans Supply Chain, Semiconductors, Networks, IoT, Security, and Smart Cities. He holds an MEng, Electrical and Electronics Engineering from The Ohio State University.
Enhancing your RISC-V SoC debug and optimization with embedded functional monitors
T1.5.10, Tuesday 13 at 15:16, in Gaston Berger amphitheater (S2).
By Mat O’Donnell, Software Architect Lead, Siemens.
Abstract: A modern RISC-V SoC may have up to several thousand embedded processor cores, running highly optimized software workloads in the field. Time-to-market pressures, system performance and in-field reliability requirements drive a need for high visibility into large fleets of deployed devices executing real-life software workloads. Traditional debug solutions are typically not built for the complexity seen in today’s complex SoCs. In this presentation, we will explain how a scalable system of embedded functional monitors combined with embedded and host/cloud based analytic software can provide actionable data and insights that helps debug, validate, and optimize RISC-V SoC devices and systems from lab bring-up to reliable large scale deployment.
Bio: Mat O’Donnell is a Software Architect Tech Lead at Tessent Embedded Analytics, Siemens EDA. Mat has 25 years of experience working in the Software Industry across multiple successful startups. In March 2017 Mat joined Tessent Embedded Analytics providing software solutions for its embedded silicon IPs where he leads a team of engineers specializing in efficient host-based software support for functional monitoring.
Cloud based RISC-V servers: How and why we built them, how you can use them
T2.1.01, Wednesday 14 at 09:00, in Gaston Berger amphitheater (S2).
By Fabien Piuzzi, R&D Engineer, Scaleway.
Abstract: Tasked with investigating the readiness of RISC-V servers, Scaleway Labs identified the lack of readily available RISC-V servers as a missing piece for the wider RISC-V ecosystem. Based on recently released hardware, Scaleway launched the first cloud based RISC-V offer, making it available to everyone in a few clicks and a few minutes. This presentation outlines the motivation, challenges, and technical efforts behind this initiative, detailing the process from research to deployment and the lessons learned. We also discuss the future of RISC-V in datacenters and our expectations from hardware manufacturers to accelerate RISC-V adoption. Scaleway, founded in 1999, provides managed solutions for bare metal, containerization, and serverless, offering a robust, scalable infrastructure for AI and machine learning workloads, and is recognized as a key innovator in this domain in Europe.
Bio: Fabien Piuzzi is an R&D Engineer at the cloud provider Scaleway, where he leads the company’s RISC-V initiatives. With over 20 years of experience in open source software and hardware, he has a strong background in Linux servers, embedded systems, and a particular focus on energy efficiency. As part of his role, he has been tasked with assessing the readiness of RISC-V for server applications and led Scaleway’s project to launch the first cloud-based RISC-V servers in 2024.
XiangShan KMHv2: An Open Source RISC-V Core with >15/GHz for SPECCPU2006
T2.1.03, Wednesday 14 at 09:30, in Gaston Berger amphitheater (S2).
By Yungang Bao, Deputy director of ICT/CAS and Chief Scientist of Beijing Institute of Open Source Chip , BOSC.
Abstract: Xiangshan is an open-source high-performance RISC-V core that was initiated in 2020 (http://github.com/OpenXiangShan/XiangShan). After five years of development, Xiangshan has undergone three architectural upgrades and four tape-outs, all of which have met the expected performance targets. Currently, the latest generation of Xiangshan KMHv2, has completed its RTL design and verification, achieving a performance score of 15/GHz for SPECCPU2006, with comprehensive performance close to that of ARM Neoverse N2. It has already been delivered to companies for SoC development. Notably, not only is the RTL codes of Xiangshan itself open-source, but a series of development and verification tools are also open-source. More information will be introduced in the talk.
Bio: Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. He is leading the XiangShan project (http://github.com/OpenXiangShan/XiangShan), which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019. His work was published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, MICRO etc. and was selected to IEEE Micro Top Picks. He was the winner of CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.
The case for Open Source Hardware at Thales: Motivations and Recent Miletones with CVA6
T2.1.05, Wednesday 14 at 10:00, in Gaston Berger amphitheater (S2).
By Bernhard Quendt, Chief Technical Officer Thales Group, Thales.
Abstract: ( need more time)
Bio: Dr. Bernhard Quendt holds engineering degrees from the University of Stuttgart and Télécom Paris (ENST), and completed a PhD at the Technical University of Munich, where he was awarded the Rohde & Schwarz Prize. Formerly Chief Technical Officer for Siemens Digital Industries, Dr. Bernhard Quendt joined the Siemens Communications division in 1999 before being appointed Vice President R&D for Siemens Rail Automation in 2005. In 2011 he took the responsibility for platform activities and R&D as Vice President for Siemens Industrial Automation Systems and since 2015, he held the position of the Chief Technical Officer at Siemens Digital Industries. Bernhard Quendt joined Thales in 2020 as Chief Technical Officer and Senior Vice President.
A Safe Software Convergence: How Automotive and Industrial Designs are Eliminating Boundaries and Creating Opportunities
T2.3.01, Wednesday 14 at 11:30, in Gaston Berger amphitheater (S2).
By Edward Wilford, Senior Research Manager, Omdia.
Abstract: For decades, the automotive sector has been considered something of an island, with a high moat and a unique development cycle. However, in recent years and spurred mainly by a rich crop of new entrants from China, automotive technology has accelerated and broadened. A new focus on more general-purpose compute, driven by a software-first approach, has as an unintended but beneficial consequence opened up the barriers between automotive and industrial applications, and paved the way for product development shaped more by function than application. This talk will demonstrate that the various software-defined system revolutions are in fact a single phenomenon happening across industries, anywhere where advanced edge deployments are on the rise. Furthermore, why this presents itself as a unique opportunity for RISC-V will be discussed.
Bio: Edward is the Senior Research Director, Automotive, at Wards Intelligence and Omdia Automotive, having previously covered automotive AI and semiconductors as Omdia’s Senior Principal Analyst, IoT. He has written extensively on embedded applications processors, edge AI, advanced connectivity, and novel semiconductor architectures such as RISC-V. He started in the industry in 2016 when he joined Arm as a market intelligence analyst, leading market research and forecasting in the automotive and IoT division. He has also worked in financial services and media roles in London. He has a BA from Durham University and an MPhil in Linguistics from the University of Cambridge.
RISC-V: Powering the Future of High Performance Computing?
T2.5.01, Wednesday 14 at 14:30, in Gaston Berger amphitheater (S2).
By Nick Brown, Senior Research Fellow, ECC.
Abstract: For all it’s successes in embedded computing, RISC-V is yet to become mainstream in High Performance Computing (HPC). However, times are changing and at the same time that RISC-V is making progress towards more high end usage, the HPC community is facing unprecedented challenges around meeting the demand for increased performance but in a more sustainable manner. RISC-V has an opportunity to displace entrenched technologies here, and in this talk I will highlight the key benefits that RISC-V can provide to HPC, describe some of the important activities and early achievements in this area, and identify critical missing pieces that we as the RISC-V community should look to prioritise.
Bio: I am interested in the role that novel hardware can play in future supercomputers, and am specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively exploit such technologies without extensive hardware/architecture expertise. My research combines novel algorithmic techniques for this new hardware, programming language & library design, and compilers. I coordinate knowledge exchange for the ExCALIBUR exascale software programme, and chair the RISC-V International HPC SIG. I head up EPCC’s PhD programme and am course organiser for the in-person and online Parallel Design Patterns MSc modules. I am currently undertaking a Royal Society of Edinburgh personal research fellowship.
From Open Silicon to Sovereign Supercomputing: EuroHPC's Vision for RISC-V
T2.5.02, Wednesday 14 at 14:45, in Gaston Berger amphitheater (S2).
By Alexandra Kourfali, Program Manager, EuroHPC.
Abstract: The EuroHPC Joint Undertaking is transforming Europe’s supercomputing landscape. EuroHPC initiatives aim to facilitate open-source HPC innovation using HW/SW co-design, advanced nodes, and cutting-edge technologies. Central to this vision lay two flagship EuroHPC initiatives focused on developing high-performance RISC-V processors and accelerators. RISC-V is uniquely positioned to power the next generation of HPC systems, as an open and extensible instruction set architecture. This talk will explore how the RISC-V ISA and the EuroHPC flagships are laying the groundwork for a new class of European supercomputers — energy-efficient, scalable, sovereign, and built for the future.
Bio: Alexandra Kourfali is a program manager of research and innovation at the EuroHPC Joint Undertaking. She received her Computer Engineering diploma from the University of Thessaly, Greece, and her Ph.D. in Computer Engineering from Ghent University, Belgium. She has worked in research, development, and innovation for a decade in academia and the private sector in Belgium, the Netherlands, Spain, Germany, and Luxembourg. Her research experience ranges from HPC, reconfigurable, and approximate computing to hardware reliability and computer architectures. Since she joined EuroHPC, she has been managing the chips projects with a strong focus on the RISC-V initiatives
Chips JU and the Vehicle of the Future – a RISC V view
T2.7.01, Wednesday 14 at 16:30, in Gaston Berger amphitheater (S2).
By Georgi Kuzmanov, Senior Programme Officer, Chips JU.
Abstract: The Chips Joint Undertaking (JU) was established in September, 2023, to implement the Chips for Europe Initiative, the first pillar of the European Chips Act and to continue the missions of its preceding joint technology initiatives in the field of electronic components and systems (ECS). For several years now, the Chips JU has been supporting two topics of common European interest, namely– Software Defined Vehicle (SDV) and RISC V based design of ECS. These two topics, initially pursued independently, have naturally converged into joint actions targeting the development of industrially significant RISC V based platforms, which support the digital Vehicle-of-the-Future (VoF) paradigm. This talk will reveal the evolution and the current state-of-play of Chips JU’s activities in the fields of SDV and RISC V. The context will be the inevitable transformation of traditional automotive industry towards digitalization to meet the global challenges in the sector. Chips JU’s vision to employ RISC V based systems supporting SDV via hardware abstraction and consequently building a holistic digital platform for the VoF will be argued. This approach is seen as an advantageous strategic choice with significant potential impact, leading towards European technological sovereignty and more cost-efficient, thus more competitive and innovative, car manufacturing.
Bio: Dr. Georgi Kuzmanov obtained an engineering degree in Computer Systems from TU Sofia, Bulgaria and a PhD degree in Computer Engineering from TU Delft, the Netherlands, in 1998 and 2004 respectively. He started his professional career in industry as an IP and processor design engineer in 1997. Between 2000 and 2011, he was a researcher and a faculty member of the EEMCS faculty at TU Delft, where he is still lecturing. Since 2011, Georgi Kuzmanov has been serving as a programme officer for the ARTEMIS Joint Undertaking (JU), the ECSEL JU, the KDT JU, and recently the Chips JU. He has authored and co-authored nearly a hundred scientific publications, mainly in the fields of computer architecture and microarchitecture. His portfolio as a programme officer includes JU-funded projects on high-performance computing, RISC V, safety critical cyber-physical systems, software-defined vehicle, edge AI, neuromorphic chip design, and quantum computing, to name a few.
Open Source Chip Design in the European Semiconductor Strategy
T3.1.01, Thursday 15 at 09:00, in Gaston Berger amphitheater (S2).
By Stefan Wallentowitz, Professor, Hochschule München & FOSSi Foundation.
Abstract: Open source chip design has become part of the European strategy, particularly focusing on sovereignty, design access, productivity and talent. In this presentation, you will learn about open source chip design in Europe, how RISC-V plays an integral role in there and ongoing activities.
Bio: Stefan is a professor of Computer Engineering at Hochschule München University of Applied Sciences. He serves as vice-chair of the RISC-V board of directors and is director at FOSSi Foundation. He is a long term advocate of open standards and open source chip design.
RISC-V: Reaching New Orbits in Space Computing
T3.3.01, Thursday 15 at 11:30, in Gaston Berger amphitheater (S2).
By Lucana Santos, Microelectronics Engineer, ESA.
Abstract: RISC-V in space is becoming a tangible reality, with several missions already flying it. This presentation highlights the European Space Agency (ESA) latest developments to advance the adoption of this open-source instruction set architecture (ISA) in space systems. The portfolio of RISC-V centred System-on-Chip (SoC) for space is growing, with new devices soon going to be manufactured and offered in the market. Such SoCs bring unique space-related features as well as technical and programmatical challenges, which are presented in this talk. RISC-V in space is further supported by ESA by promoting the design and implementation of high-performance, reliable IP cores, and the establishment of a robust software ecosystem. In addition, the Ultra Deep Submicron (UDSM) initiative will be presented, showing how advanced semiconductor technology development is further accelerating the integration of RISC-V into space-grade electronics. These advancements will enable future space missions and projects to fully leverage the benefits of an open, flexible, and scalable ISA, fostering innovation, reducing dependency on proprietary technologies, and enhancing long-term sustainability in the space industry.
Bio: Lucana Santos got her PhD in Telecommunications at the University of Las Palmas de Gran Canaria. She has several years of experience as researcher in the field of digital design for data processing on FPGAs and heterogeneous computing. She currently holds a position as Microelectronics Engineer for the European Space Agency, with a strong focus on digital IP and microprocessor design.
The Significance of the RVA23 Profile in Advancing RISC-V Ecosystem
T3.5.01, Thursday 15 at 14:30, in Gaston Berger amphitheater (S2).
By Mark Hayter, Chief Strategy Officer & Co-Founder, RIVOS.
Abstract: The RVA23 profile represents a key development in the RISC-V architecture, standardizing the 64-bit application processors ISA for seamless software portability across hardware implementations. This simplifies development and supports RISC-V adoption in areas like servers, automotive and client devices, where binary compatibility is important. This presentation will look at the impact RVA23 and the platform specifications will have on high-performance applications processors and their adoption across a range of end use cases.
Bio: Mark Hayter is Chief Strategy Officer & Co-Founder of Rivos Inc. For the previous 11 years he was Senior Engineering Director in the Chrome OS Hardware team at Google. His team developed new technologies for Chromebooks, produced reference implementations and worked with OEMs to bring them to market. Prior to that he was involved in systems architecture at several semiconductor companies, being VP of Systems Engineering at P.A. Semi, Inc. (acquired by Apple Inc.), Senior Manager of Hardware Systems Engineering at Broadcom Corporation and System Architect at SiByte, Inc. Earlier, Hayter was at the Digital Equipment Corporation Systems Research Center. Hayter holds a PhD from the University of Cambridge Computer Laboratory.
RISC-V open designs and contributions to hardware security research and development activities
T3.7.01, Thursday 15 at 16:30, in Gaston Berger amphitheater (S2).
By Éric Saliba, Head of Scientific & Technical Division, ANSSI.
Abstract: This presentation provides a perspective on the technical challenges of securing components and the opportunities offered by open designs based on RISC-V, giving some recent examples of ANSSI contributions to open source projects or funded projects.
Bio: Éric Saliba is head of the Scientific and Technical Division of the French National Agency for Information Systems Security (ANSSI), which brings together laboratories that contribute to the definition and maintenance of the Agency’s technical guidelines and recommendations, and provides their expertise to its beneficiaries. Eric had worked for over twenty years on upstream studies and major research and development projects, both as an expert and technical manager.